Write tracking circuits for memory cells provide signals based on which write signals for a memory cell having data written therein are generated. Generally, the write tracking circuits are designed such that the worst case condition for writing to the memory cell is covered.
In one existing method for tracking write signals of a memory cell, a signal path for a tracking write bit line is similar to a signal path for a write bit line of the memory cell. When the tracking write bit line is pulled down to about half of the operational voltage of the memory cell, a signal to reset the write signals for the memory cell is activated. In various conditions, the tracking timing does not cover the worst case timing for the memory cell.
Like reference symbols in the various drawings indicate like elements.